Note: The job is a remote job and is open to candidates in USA. Synopsys provides engineering solutions spanning silicon to systems, including silicon design, IP, simulation, analysis, and design services for AI-powered products. The Senior Staff ASIC Design Engineer will develop and maintain PHYINIT configuration software and embedded firmware for DDR PHY IP, collaborate with design and verification teams, debug silicon bring-up issues, and improve automation and release processes.

Responsibilities

• Design, develop, and maintain PHYINIT, the configuration software that initializes and configures Synopsys DDR PHY IP across multiple product generations
• Write runtime firmware that runs on embedded controllers within the PHY, managing training sequences, calibration, and operational modes
• Collaborate directly with digital design and verification engineers to enable new DDR features, translating RTL changes into working configuration code
• Debug PHY bring-up issues on customer silicon and internal test chips, analyzing register states, firmware logs, and waveforms to isolate root causes
• Build and improve automation flows using Python or Perl to generate configuration code, validate settings, and streamline integration into customer SoCs
• Own the software/firmware release process for PHYINIT, ensuring compatibility across design revisions and customer use cases
• Participate in architecture discussions for future PHY generations, representing the software and firmware perspective early in the design cycle

Skills

• Bachelor's degree in electrical engineering, Computer Engineering, or equivalent practical experience
• 5+ years of hands-on experience in ASIC design, verification, or firmware development, ideally involving configuration or bring-up work
• Strong C programming skills with experience writing firmware or embedded software for hardware systems
• Solid understanding of data structures, algorithms, and software design principles applied to hardware configuration problems
• Proficiency in scripting languages like Python or Perl for automation, code generation, or build flows
• Proven debugging skills across multiple layers, firmware, RTL, registers, and silicon behavior
• You can read RTL well enough to understand what a configuration register does, not just what the spec says it should do
• You write code that other engineers can debug six months later without needing you in the room
• When a bring-up fails, you methodically work through failure, checking assumptions and isolating variables instead of guessing
• You communicate clearly with design engineers who think in Verilog and verification engineers who think in test benches, translating between their worlds and yours
• You push back when a new feature is underspecified from a software perspective, and you do it early enough to matter
• You are comfortable working across time zones with a global team, and you document your work in a way that makes asynchronous collaboration work
• Experience with high-speed interface protocols such as DDR, LPDDR, or other memory standards is a strong plus

Benefits

• Health benefits
• Wellness benefits
• Financial benefits
• Monetary and non-monetary total rewards

Company Overview

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